Many data processing systems use multiple processor boards for permitting the performance of different processing tasks simultaneously by different ones of the system's processors. Such systems require an appropriate commonly used system address/data bus and system bus control for handling address and data transfers between the processors and other units on the bus such as memory units and various input/output (I/O) devices. Such bus systems are normally controlled in a synchronous manner so that the interactions of the operations of such units can be effectively handled on the common bus system. Over time, various units on the bus may be redesigned to provide improved performance characteristics, e.g., the speeds of operation thereof may be improved so that operations can be completed more quickly, there often being several successive generations of such improved components. Such improvements normally require a substantially redesigned bus system in order to provide for the appropriate handling of address and data transfers among units having different operating speeds than those for which the bus system was originally designed.
Moreover, in such synchronously operated systems, arbitration among units competing for access to the bus system for address and data transfers thereon must be completed for each unit in control of the bus before another unit can take control of the bus to perform its task or, alternatively, the operations of different units must be suitably synchronously interleaved so that one unit can make use of the bus system for address transfer, while another unit makes use of the bus for data transfer, neither operations being performed until priority among units competing for access to the bus system has been activated.
It is desirable to provide a bus system and bus control therefor which does not require substantial redesign thereof as improved components become available for use with the bus system so that the bus system and its operation, once designed, can remain usable, and does not become obsolescent, for several successive generations of improved system component designs. Moreover, it is desirable to provide a bus system which can permit arbitration, address transfer, and data transfer operations to occur simultaneously for different processors performing different processing tasks in an efficiently controlled manner.